The present invention relates to a method of executing a computer program and to a computer system.
A computer system is described which comprises a plurality of parallel execution units which are responsible for carrying out the operations defined in a computer program. The computer program consists of a sequence of program instructions. In the computer system described herein, the format of the program instructions is selectable in dependence on an instruction mode of the computer system. The computer system can operate in a number of different instruction modes (three in the described example). It is desirable however that the execution units can execute instructions independently of the operational mode of the computer system.
To achieve this, the present invention provides a computer system comprising: a memory holding a computer program consisting of a sequence of program instructions, the format of the program instructions being selectable in dependence on an instruction mode of the computer system; a decoder arranged to receive and decode program instructions from the memory; a microinstruction generator responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format having a plurality of fields of respectively fixed lengths allocated to hold certain data derived from the program instructions, the microinstruction format being independent of the instruction mode of the computer system; and a plurality of parallel execution units for receiving and executing said microinstructions.
Another aspect of the invention provides a method of executing a computer program consisting of a sequence of program instructions held in a memory of a computer system, wherein the format of the program instructions is selectable in dependence on an instruction mode of the computer system, the method comprising: decoding said program instructions; generating microinstructions responsive to information from the decoded program instructions according to a predetermined microinstruction format having a plurality of fields of respectively fixed length allocated to hold certain data derived from the program instructions, the microinstruction format being independent of the instruction mode of the computer system; and supplying said microinstructions to one or more of a plurality of parallel execution units for receiving and executing said microinstructions.
In the particular computer system described herein, the execution units comprise a first set of execution pipelines for use in executing microinstructions needed for memory access operations and a second set of execution pipelines arranged to carry out arithmetic operations thereby providing decoupling of memory access operations from arithmetic operations. This is particularly suited to provide a high digital signal processing performance.
Preferably there is a first microinstruction format for use for microinstructions supplied to the first set of execution pipelines and a second microinstruction format for use for microinstructions supplied to the second set of execution pipelines.
The microinstructions sent to the execution units have a plurality of different fields of respectively fixed lengths.
These fields hold data derived from the program instructions, including for example register names and their validity bits, opcodes, source guards, destination guards etc. Source guards and destination guards relate to a mechanism for executing guarded instructions which is not described further herein.
Some program instructions include an immediate value, which in an actual embodiment can be up to 25 bits for address unit instructions and 16 bits for data unit instructions. In many cases, these immediate values need to be supplied to the execution units for use in execution of the microinstructions. Prior to execution by the execution units, the microinstructions can be held in instruction queues associated respectively with the execution units. The size of the queues depends on the size of the microinstructions. If the microinstructions had a field specifically allocated to receive the immediate value, and had the maximum length possible for the immediate value, then the size of these queues, and also the size of the silicon needed to implement the computer system, would increase. Moreover, for much of the time these fields would remain unused.
Therefore, an additional aspect of the present invention is to provide that the microinstruction generator locates the immediate value in the microinstructions in one or more of said fixed length fields in place of the data normally allocated to the fields. In a program instruction using an immediate value, this immediate value takes the place of other data in the program instruction, for example register values. Thus, these fields of the microinstruction become available for holding the immediate value. Valid fields of the microinstruction never contain an immediate value.
The computer system can operate in one of a number of instruction modes, as mentioned above. The number of microinstructions generated in each machine cycle varies in dependence on the instruction mode of the computer system. In a computer system having four parallel execution units, a maximum of four microinstructions is generated per machine cycle.
The computer system can have a prefetcher for fetching instructions from the memory and supplying them to the decoder. The prefetcher is controlled so that the number and length of instructions fetched from the memory in each machine cycle depends on the instruction mode of the computer system.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings.